A low-power mode of operation for microprocessors is becoming increasingly important as more portable products and battery operated products are developed for consumers. Typically a low power mode will disable or tri-state external pins of the integrated circuit (IC) to eliminate current drain due to voltage mismatches between external pins and internal circuitry and disable/stop clocks to reduce switching and power drain over time. In order to exit a low power mode of operation, typically an external signal or an interrupt is input to the integrated circuit and the integrated circuit "wakes up" in response to this external signal or interrupt. "Waking up" is usually referring to enabling/restarting the clock and bringing the IC pins out of their tri-state configuration.
One problem with low power modes is that low power modes are difficult to test and verify in the manufacturing phase. Once a low power mode is entered it is clear that the integrated circuit has no accessible inputs/outputs (all of them have been tri-stated) and have no clock in which to switch states or operate. A design defect, manufacturing defect, or like defect(s) could result in the interrupt or external signal being missed, mis-processed, electrically short-circuited, or the like resulting in the part being stuck in a low power mode forever. A designer cannot determine what went wrong with the integrated circuit since the designer cannot access the part due to tri-stated inputs, outputs, and I/O pins and disabled clock. Therefore, a need exists, for system diagnostic and test purposes, to allow for testing an integrated circuit while in low power mode, allow for verification of low power operation before entrance into low power mode, and to allow a way to force-exit a low power mode in order to access more internal information in the case of a defect. In conventional ICs, the inclusion of low power test circuitry does not allow an IC to attain a lowest-possible low power mode, which is disadvantageous .